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MTP29N15E
Preferred Device
Power MOSFET 29 Amps, 150 Volts
N-Channel TO-220
This Power MOSFET is designed to withstand high energy in the avalanche and commutation modes. The energy efficient design also offers a drain-to-source diode with a fast recovery time. Designed for low voltage, high speed switching applications in power supplies, converters and PWM motor controls. These devices are particularly well suited for bridge circuits where diode speed and commutating safe operating areas are critical and offer additional safety margin against unexpected voltage transients. * Avalanche Energy Specified * Source-to-Drain Diode Recovery Time Comparable to a Discrete Fast Recovery Diode * Diode is Characterized for Use in Bridge Circuits * IDSS and VDS(on) Specified at Elevated Temperature
MAXIMUM RATINGS (TC = 25C unless otherwise noted)
Rating Drain-to-Source Voltage Drain-to-Gate Voltage (RGS = 1.0 M) Gate-to-Source Voltage - Continuous - Non-Repetitive (tp 10 ms) Drain Current - Continuous Drain Current - Continuous @ 100C Drain Current - Single Pulse (tp 10 s) Total Power Dissipation Derate above 25C Operating and Storage Temperature Range Single Pulse Drain-to-Source Avalanche Energy - Starting TJ = 25C (VDD = 25 Vdc, VGS = 10 Vdc, Peak IL = 29 Apk, L = 1.0 mH, RG = 25 W) Thermal Resistance - Junction to Case - Junction to Ambient Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds Symbol VDSS VDGR VGS VGSM ID ID IDM PD TJ, Tstg EAS Value 150 150 20 40 29 19 102 125 1.0 -55 to 150 421 Unit Vdc Vdc Vdc Vpk Adc Apk Watts W/C C mJ 2 Drain C/W RJC RJA TL 1.0 62.5 260 C MTP29N15E LL Y WW = Device Code = Location Code = Year = Work Week 1 2 TO-220AB CASE 221A STYLE 5 4 S
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29 AMPERES 150 VOLTS RDS(on) = 70 m
N-Channel D
G
MARKING DIAGRAM & PIN ASSIGNMENT
4 Drain
MTP29N15E LLYWW 3 Source
3
1 Gate
ORDERING INFORMATION
Device MTP29N15E Package TO-220AB Shipping 50 Units/Rail
Preferred devices are recommended choices for future use and best overall value.
(c) Semiconductor Components Industries, LLC, 2000
1
November, 2000 - Rev. 2
Publication Order Number: MTP29N15E/D
MTP29N15E
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)
Characteristic OFF CHARACTERISTICS Drain-to-Source Breakdown Voltage (VGS = 0 Vdc, ID = 0.25 mAdc) Temperature Coefficient (Positive) Zero Gate Voltage Drain Current (VDS = 150 Vdc, VGS = 0 Vdc) (VDS = 150 Vdc, VGS = 0 Vdc, TJ =125C) Gate-Body Leakage Current (VGS = 20 Vdc, VDS = 0 Vdc) ON CHARACTERISTICS (Note 1.) Gate Threshold Voltage (VDS = VGS, ID = 250 Adc) Threshold Temperature Coefficient (Negative) Static Drain-to-Source On-Resistance (VGS = 10 Vdc, ID = 14.5 Adc) Drain-to-Source On-Voltage (VGS = 10 Vdc, ID = 29 Adc) (VGS = 10 Vdc, ID = 14.5 Adc, TJ = 125C) Forward Transconductance (VDS = 8.6 Vdc, ID = 14.5 Adc) DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance Transfer Capacitance SWITCHING CHARACTERISTICS (Note 2.) Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Gate Charge (VDS = 120 Vdc, ID = 29 Adc, VGS = 10 Vdc) (VDD = 75 Vdc, ID = 29 Adc, VGS = 10 Vdc, Vdc RG = 9.1 ) td(on) tr td(off) tf QT Q1 Q2 Q3 SOURCE-DRAIN DIODE CHARACTERISTICS Forward On-Voltage (IS = 29 Adc, VGS = 0 Vdc) (IS = 29 Adc, VGS = 0 Vdc, TJ = 125C) Reverse Recovery Time (IS = 29 Adc, VGS = 0 Vdc, Adc Vdc dIS/dt = 100 A/s) Reverse Recovery Stored Charge INTERNAL PACKAGE INDUCTANCE Internal Drain Inductance (Measured from contact screw on tab to center of die) (Measured from the drain lead 0.25 from package to center of die) Internal Source Inductance (Measured from the source lead 0.25 from package to source bond pad) 1. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 2. Switching characteristics are independent of operating junction temperature. LD - - LS - 7.5 - 3.5 4.5 - - nH trr ta tb QRR VSD - - - - - - 0.92 0.84 174 126 48 1.4 1.3 - - - - - C ns Vdc - - - - - - - - 19 95 90 85 83 12 37 23 40 190 180 170 120 - - - nC ns (VDS = 25 Vd VGS = 0 Vdc, Vdc, Vd f = 1.0 MHz) Ciss Coss Crss - - - 2300 450 130 3220 630 260 pF VGS(th) 2.0 - RDS(on) - VDS(on) - - gFS 10 - - 20 2.4 2.1 - mhos 0.054 0.07 Vdc 2.7 5.4 4.0 - Vdc mV/C Ohms V(BR)DSS 150 - IDSS - - IGSS - - - - 10 100 100 nAdc - 151 - - Vdc mV/C Adc Symbol Min Typ Max Unit
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TYPICAL ELECTRICAL CHARACTERISTICS
60 60 ID, DRAIN CURRENT (AMPS) 50 40 30 20 10 9 10 0 2 3 TJ = 100C -55C 4 5 6 7 8 25C
ID , DRAIN CURRENT (AMPS)
VGS = 10 V 9V 50 TJ = 25C 8V 40 30 20 10 0 0 1 2 3 4 5
7V
6.5 V
VDS 10 V
6V
5.5 V 5V 4.5 V 4V 6 7 8 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)
VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)
Figure 1. On-Region Characteristics
RDS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS) RDS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS)
Figure 2. Transfer Characteristics
0.14 0.12 0.10 0.08 0.06 0.04 0.02 0 0
VGS = 10 V TJ = 100C
0.07 0.065 0.06 0.055 0.05 0.045 0.04 0 10 20 40 30 ID, DRAIN CURRENT (AMPS) 50 60 TJ = 25C VGS = 10 V 15 V
25C
-55C
10
20
30
40
50
60
ID, DRAIN CURRENT (AMPS)
Figure 3. On-Resistance versus Drain Current and Temperature
2.25 2.0 1.75 1.5 1.25 1.0 0.75 0.5 0.25 0 -50 -25 0 25 50 75 100 125 150 0.1 0 VGS = 10 V ID = 14.5 A IDSS , LEAKAGE (nA) 100 1000
Figure 4. On-Resistance versus Drain Current and Gate Voltage
RDS(on) , DRAIN-TO-SOURCE RESISTANCE (NORMALIZED)
VGS = 0 V
TJ = 125C 100C
10
25C
1
20
TJ, JUNCTION TEMPERATURE (C)
60 80 40 100 120 140 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)
160
Figure 5. On-Resistance Variation with Temperature
Figure 6. Drain-To-Source Leakage Current versus Voltage
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MTP29N15E
POWER MOSFET SWITCHING Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because drain-gate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG - VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turn-on and turn-off delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG - VGSP)] td(off) = RG Ciss In (VGG/VGSP)
7500 VDS = 0 V VGS = 0 V 7000 6500 Ciss 6000 5500 5000 Crss 4500 4000 3500 3000 2500 2000 1500 1000 Crss 500 0 -10 -5 0 5 VGS VDS
The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the off-state condition when calculating td(on) and is read at a voltage corresponding to the on-state when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses.
TJ = 25C
C, CAPACITANCE (pF)
Ciss
Coss 10 15 20 25
GATE-TO-SOURCE OR DRAIN-TO-SOURCE VOLTAGE (VOLTS)
Figure 7. Capacitance Variation
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VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) 10 9 8 7 6 5 4 3 2 1 0 Q3 0 10 20 30 40 50 VDS 60 70 80 90 Qg, TOTAL GATE CHARGE (nC) TJ = 25C ID = 29 A Q1 Q2 QT VGS 120 100 80 60 40 20 0 1000 VDS , DRAIN-TO-SOURCE VOLTAGE (VOLTS)
100 t, TIME (ns)
tf td(off) td(on)
tr
10
1
1
10 RG, GATE RESISTANCE (OHMS)
100
Figure 8. Gate-To-Source and Drain-To-Source Voltage versus Total Charge
Figure 9. Resistive Switching Time Variation versus Gate Resistance
DRAIN-TO-SOURCE DIODE CHARACTERISTICS The switching characteristics of a MOSFET body diode are very important in systems using it as a freewheeling or commutating diode. Of particular interest are the reverse recovery characteristics which play a major role in determining switching losses, radiated noise, EMI and RFI. System switching losses are largely due to the nature of the body diode itself. The body diode is a minority carrier device, therefore it has a finite reverse recovery time, trr, due to the storage of minority carrier charge, QRR, as shown in the typical reverse recovery wave form of Figure 15. It is this stored charge that, when cleared from the diode, passes through a potential and defines an energy loss. Obviously, repeatedly forcing the diode through reverse recovery further increases switching losses. Therefore, one would like a diode with short trr and low QRR specifications to minimize these losses. The abruptness of diode reverse recovery effects the amount of radiated noise, voltage spikes, and current ringing. The mechanisms at work are finite irremovable circuit parasitic inductances and capacitances acted upon by
30 I S , SOURCE CURRENT (AMPS) 25 20 15 10 5 0 0.6 0.65 0.7 0.75 0.8 0.85 0.9 0.95 VGS = 0 V TJ = 25C
high di/dts. The diode's negative di/dt during ta is directly controlled by the device clearing the stored charge. However, the positive di/dt during tb is an uncontrollable diode characteristic and is usually the culprit that induces current ringing. Therefore, when comparing diodes, the ratio of tb/ta serves as a good indicator of recovery abruptness and thus gives a comparative estimate of probable noise generated. A ratio of 1 is considered ideal and values less than 0.5 are considered snappy. Compared to ON Semiconductor standard cell density low voltage MOSFETs, high cell density MOSFET diodes are faster (shorter trr), have less stored charge and a softer reverse recovery characteristic. The softness advantage of the high cell density diode means they can be forced through reverse recovery at a higher di/dt than a standard cell MOSFET diode without increasing the current ringing or the noise generated. In addition, power dissipation incurred from switching the diode will be less due to the shorter recovery time and lower switching losses.
VSD, SOURCE-TO-DRAIN VOLTAGE (VOLTS)
Figure 10. Diode Forward Voltage versus Current
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MTP29N15E
di/dt = 300 A/s I S , SOURCE CURRENT Standard Cell Density trr High Cell Density trr tb ta
t, TIME
Figure 11. Reverse Recovery Time (trr)
SAFE OPERATING AREA The Forward Biased Safe Operating Area curves define the maximum simultaneous drain-to-source voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, "Transient Thermal Resistance - General Data and Its Use." Switching between the off-state and the on-state may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded, and that the transition time (tr, tf) does not exceed 10 s. In addition the
1000 EAS , SINGLE PULSE DRAIN-TO-SOURCE AVALANCHE ENERGY (mJ) ID , DRAIN CURRENT (AMPS) VGS = 20 V SINGLE PULSE TC = 25C 10 ms 100 ms 1 ms 10 ms dc
total power averaged over a complete switching cycle must not exceed (TJ(MAX) - TC)/(RJC). A power MOSFET designated E-FET can be safely used in switching circuits with unclamped inductive loads. For reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and must be adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases non-linearly with an increase of peak current in avalanche and peak junction temperature.
450 400 350 300 250 200 150 100 50 0 25 50 75 100 125 150 ID = 29 A
100
10
1
RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 0.1 1 10 100
0.1
1000
VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)
TJ, STARTING JUNCTION TEMPERATURE (C)
Figure 12. Maximum Rated Forward Biased Safe Operating Area
Figure 13. Maximum Avalanche Energy versus Starting Junction Temperature
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TYPICAL ELECTRICAL CHARACTERISTICS
1 r(t), EFFECTIVE TRANSIENT THERMAL RESISTANCE (NORMALIZED) D = 0.5 0.2 0.1 0.1 0.05 0.02 0.01 0.01 SINGLE PULSE 1E-05 1E-04 1E-03 1E-02 t, TIME (seconds) P(pk) t2 DUTY CYCLE, D = t1/t2 1E-01 t1 RJA(t) = r(t) RJA D CURVES APPLY FOR POWER PULSE TRAIN SHOWN READ TIME AT t1 TJ(pk) - TA = P(pk) RJA(t) 1E+00 1E+01
Figure 14. Thermal Response
di/dt IS trr ta tp IS tb TIME 0.25 IS
Figure 15. Diode Reverse Recovery Waveform
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MTP29N15E
TYPICAL SOLDER HEATING PROFILE For any given circuit board, there will be a group of control settings that will give the desired heat pattern. The operator must set temperatures for several heating zones and a figure for belt speed. Taken together, these control settings make up a heating "profile" for that particular circuit board. On machines controlled by a computer, the computer remembers these profiles from one operating session to the next. Figure 16 shows a typical heating profile for use when soldering a surface mount device to a printed circuit board. This profile will vary among soldering systems, but it is a good starting point. Factors that can affect the profile include the type of soldering system in use, density and types of components on the board, type of solder used, and the type of board or substrate material being used. This profile shows temperature versus time. The line on the graph shows the actual temperature that might be experienced on the surface of a test board at or near a central solder joint. The two profiles are based on a high density and a low density board. The Vitronics SMD310 convection/infrared reflow soldering system was used to generate this profile. The type of solder used was 62/36/2 Tin Lead Silver with a melting point between 177-189C. When this type of furnace is used for solder reflow work, the circuit boards and solder joints tend to heat first. The components on the board are then heated by conduction. The circuit board, because it has a large surface area, absorbs the thermal energy more efficiently, then distributes this energy to the components. Because of this effect, the main body of a component may be up to 30 degrees cooler than the adjacent solder joints.
STEP 1 PREHEAT ZONE 1 "RAMP" 200C
STEP 2 STEP 3 VENT HEATING "SOAK" ZONES 2 & 5 "RAMP"
STEP 4 HEATING ZONES 3 & 6 "SOAK"
DESIRED CURVE FOR HIGH MASS ASSEMBLIES 150C
160C
STEP 5 STEP 6 STEP 7 HEATING VENT COOLING ZONES 4 & 7 205 TO 219C "SPIKE" PEAK AT 170C SOLDER JOINT
150C 100C 100C DESIRED CURVE FOR LOW MASS ASSEMBLIES 5C 140C
SOLDER IS LIQUID FOR 40 TO 80 SECONDS (DEPENDING ON MASS OF ASSEMBLY)
TIME (3 TO 7 MINUTES TOTAL)
TMAX
Figure 16. Typical Solder Heating Profile
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MTP29N15E
PACKAGE DIMENSIONS
TO-220 THREE-LEAD TO-220AB CASE 221A-09 ISSUE AA
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION Z DEFINES A ZONE WHERE ALL BODY AND LEAD IRREGULARITIES ARE ALLOWED. DIM A B C D F G H J K L N Q R S T U V Z INCHES MIN MAX 0.570 0.620 0.380 0.405 0.160 0.190 0.025 0.035 0.142 0.147 0.095 0.105 0.110 0.155 0.018 0.025 0.500 0.562 0.045 0.060 0.190 0.210 0.100 0.120 0.080 0.110 0.045 0.055 0.235 0.255 0.000 0.050 0.045 ----0.080 GATE DRAIN SOURCE DRAIN MILLIMETERS MIN MAX 14.48 15.75 9.66 10.28 4.07 4.82 0.64 0.88 3.61 3.73 2.42 2.66 2.80 3.93 0.46 0.64 12.70 14.27 1.15 1.52 4.83 5.33 2.54 3.04 2.04 2.79 1.15 1.39 5.97 6.47 0.00 1.27 1.15 ----2.04
-T- B
4
SEATING PLANE
F T S
C
Q
123
A U K
H Z L V G D N R J
STYLE 5: PIN 1. 2. 3. 4.
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MTP29N15E
Notes
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Notes
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MTP29N15E
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer.
PUBLICATION ORDERING INFORMATION
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MTP29N15E/D

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